This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
Generally, in physical design, performance and reliability at advanced process nodes may be limited by an increase of metal resistance and via resistance as metal wires are scaled down. For instance, as metal wire width decreases, its resistance increases along with resistance of vias connecting metal wires together. Further, narrower metal wires may be sensitive to electromigration as current density increases.
In reference to physical design, FIGS. 1A-1C illustrate various diagrams of a conventional layout of a cell 100 as known in the art. In particular, FIG. 1A refers to the cell 100 with current flow during output load charge 100A, FIG. 1B refers to the cell 100 with current flow during output load discharge 100B, and FIG. 1C refers to an equivalent resistive circuit of the cell 100 with current flow during output load charge 100C.
In reference to advanced process nodes (e.g., <28 nm), a p-type field effect transistor (PFET) 110 may be coupled to an n-type FET (NFET) 112 using a local metal interconnect M0. Further, M0 may also be used to couple to VSS and VDD power rails. Another metal interconnect M1 may be an output pin of the cell 100 that may be extended in one direction (i.e., a first direction) and may be coupled to M0 using a via V0. Generally, in advanced process nodes, the output pin M1 may not be allowed to extend in a second direction (unidirectional route) that is opposite the first direction. The M1 output pin may also be coupled to other cells using a via V1 and another metal interconnect M2 during a routing step. Generally, M2 may only extend in a direction perpendicular to M1, and in advanced process nodes, M2 may not be allowed to extend in the second direction (unidirectional route). Further, whether active high or low, an activated gate (net input) allows current to flow through the transistors 110, 120 depending on type.
FIGS. 1A-1B describe different connections and resistance modeling of the cell 100. As shown, an output net resistance from M0 may be composed of V0+M1+V1+M2. Also, the M1 output pin should be implemented to sustain the current flow without significant electromigration degradation. FIG. 1A shows arrows to indicate the current flow during output load charge, e.g., when M0 (as output net coupling the NFET to the PFET) switches from 0 to 1. Further, FIG. 1B shows arrows to indicate the current flow during the output load discharge, e.g., when M0 (as the output net coupling the NFET to the PFET) switches from 1 to 0.
FIG. 1C shows an equivalent resistive network from M0 (as the output net coupling the NFET to the PFET) of the cell 100 with current flow during output load charge 100C. As shown, RV0, RM1, RV1, RM2_1 and RM2_2 are respectively V0, M1, V1 and M2 resistances. In this instance, current may be split between the M2 resistances. Therefore, total resistance between M0 and M2 may be: R1=RV0+RM1+RV1.